A plasma enhanced chemical vapor-deposited (PECVD) boron nitride (BN) film on p-type crystalline silicon (p-c-Si) was used to fabricate the metal-insulator-semiconductor (MIS) test structure. The effects of positive (inverting type) and negative (accumulating type) bias stresses on the MIS (Al/BN/p-Si/Al) structure were investigated as a function of time, bias voltage stresses and temperature. Charge injection into the gate dielectric (BN film in this case) was considered as a mechanism to provoke the instability problem that manifested itself as a slow shift of specific voltage (Delta V-HH) which symbolizes the whole capacitance-gate bias voltage (C-V) curve. Moreover, the evolution of this shift is followed by monitoring Delta V-HH as a function of time, temperature and gate voltage stress and fitted to a functional form for the Delta V-HH shift kinetics. Good agreement with the experimental data confirms the charge injection hypothesis behind the shift in C-V curves. Finally, the origin of an eventual defective structure, required by the actual instability, is argued in terms of possible chemical composition of the film. Seemingly BN possesses a turbostratic structure; the first layer at the initial stage in growth is amorphous (even self-doped by a contamination from the underlying silicon substrate) on which a more ordered phase might continue.