An all-silicon process platfom for wafer-level vacuum packaged MEMS devices


Torunbalci M. M. , Gavcar H. D. , Yesil F., Alper S. E. , AKIN T.

IEEE Sensors Journal, 2021 (Journal Indexed in SCI Expanded) identifier

  • Publication Type: Article / Article
  • Volume:
  • Publication Date: 2021
  • Doi Number: 10.1109/jsen.2021.3073928
  • Title of Journal : IEEE Sensors Journal

Abstract

IEEEThis paper introduces a novel, inherently simple, and all-silicon wafer-level fabrication and hermetic packaging method developed for MEMS devices. The proposed method uses two separate SOI wafers to form highly-doped through-silicon vias (TSVs) and suspended MEMS structures, respectively. These SOI wafers are then bonded by Au-Si eutectic bonding at 400°C, achieving hermetic sealing and signal transfer without requiring any complex via or trench refill process steps. The package vacuum is measured using encapsulated MEMS resonators to be as low as 15 mTorr with the help of successfully activated thin-film getters. The combined fabrication and packaging yield is around %89 and chips still maintain a package pressure below 100 mTorr after more than 6 years. The packages show an extremely high strong bonding strength (>40 MPa) and are proved to remain hermetic after temperature cycling (25°C-85°C) and harsh temperature shock (5 min@300°C) tests. The all-silicon MEMS resonators fabricated and packaged using the proposed method project up to a 2.3X enhancement in the bias instability and ~4X in the temperature sensitivity of frequency output compared to an identical MEMS resonator fabricated using the silicon-on-glass (SOG) technology.