Wafer level hermetic sealing of MEMS devices with vertical feedthroughs using anodic bonding

Torunbalci M. M., Alper S. E., AKIN T.

SENSORS AND ACTUATORS A-PHYSICAL, vol.224, pp.169-176, 2015 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 224
  • Publication Date: 2015
  • Doi Number: 10.1016/j.sna.2015.01.034
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Page Numbers: pp.169-176
  • Keywords: Wafer level hermetic packaging, Vertical feedthroughs, Anodic bonding, Advanced MEMS (aMEMS) process
  • Middle East Technical University Affiliated: Yes


This paper presents a new method for wafer-level hermetic packaging of MEMS devices using a relatively low temperature anodic bonding technique applied to the recently developed advanced MEMS (aMEMS) process. The aMEMS process uses vertical feedthroughs formed on an SOI cap wafer, eliminating the need for any complex via-refill or trench-refill steps while forming the vertical feedthroughs. The hermetic sealing process is achieved at 350 degrees C by using an anodic bonding potential of 600 V. The bonding process does not require any sealing material on neither the cap nor the sensor wafer. The packaging yield is experimentally verified to be 94% for 4 wafers packaged up to date, and the cavity pressure is measured to be as low as 1 mTorr with successfully activated Titanium thin film getter. The cavity pressure can be set to different levels ranging from 1 mTorr up to 5 Torr, simply by varying the outgassing period and utilization of the getter material, enabling the proposed method be used for various types of MEMS devices with different pressure requirements. The pressure inside the encapsulated cavities has been monitored for 6 months since the first prototypes, and it is observed that pressure is stable below 5 mTorr throughout this period. The shear strength of 6 packages is measured to be above 10 MPa, whereas the shear failure occurs not at the bonding interface but the vertical feedthroughs, which have lower strength compared to the bonding region. The robustness of the packages is tested by subjecting them to cyclic thermal tests between 100 degrees C and 25 degrees C, and no degradation is observed in the hermeticity of the packages at the end of this period. The vacuum level of the packages is also verified to be unchanged by storing the packages at 150 degrees C for 24 h. Moreover, it is experimentally verified that the hermeticity of the packaged chips can withstand ultra-high temperature shocks as high as 400 degrees C for 5 min. (C) 2015 Elsevier B.V. All rights reserved.