Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS


Yalcin T., Ismailoglu N.

32nd Asilomar Conference on Signals, Systems and Computers, California, United States Of America, 1 - 04 November 1998, pp.1066-1069 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • City: California
  • Country: United States Of America
  • Page Numbers: pp.1066-1069

Abstract

A 4-bit 64-chip Pseudo Noise (PN) coded Digital Matched Filter (DMF) is designed in 0.7um CMOS technology using Systolic Array (SA) architecture. Full-custom and full-static Cascode Voltage Switch Logic (CVSL) circuit techniques have been employed in the implementation of the basic building blocks (systoles) of the SA DMF. Significant reduction in number of transistors and power consumption have been achieved. The resultant IC is to be used at the receiver side of a wireless Direct Sequence Spread Spectrum (DSSS) communication system.