T. Yalcin And N. Ismailoglu, "Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS," 32nd Asilomar Conference on Signals, Systems and Computers , California, United States Of America, pp.1066-1069, 1998
Yalcin, T. And Ismailoglu, N. 1998. Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS. 32nd Asilomar Conference on Signals, Systems and Computers , (California, United States Of America), 1066-1069.
Yalcin, T., & Ismailoglu, N., (1998). Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS . 32nd Asilomar Conference on Signals, Systems and Computers (pp.1066-1069). California, United States Of America
Yalcin, T, And N Ismailoglu. "Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS," 32nd Asilomar Conference on Signals, Systems and Computers, California, United States Of America, 1998
Yalcin, T And Ismailoglu, N. "Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS." 32nd Asilomar Conference on Signals, Systems and Computers , California, United States Of America, pp.1066-1069, 1998
Yalcin, T. And Ismailoglu, N. (1998) . "Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS." 32nd Asilomar Conference on Signals, Systems and Computers , California, United States Of America, pp.1066-1069.
@conferencepaper{conferencepaper, author={T Yalcin And author={N Ismailoglu}, title={Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS}, congress name={32nd Asilomar Conference on Signals, Systems and Computers}, city={California}, country={United States Of America}, year={1998}, pages={1066-1069} }