A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

Torunbalci M. M. , Alper S. E. , Akın T.

JOURNAL OF MICROMECHANICS AND MICROENGINEERING, vol.25, 2015 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 25
  • Publication Date: 2015
  • Doi Number: 10.1088/0960-1317/25/12/125030
  • Keywords: advanced MEMS (aMEMS) process, wafer level hermetic packaging, vertical feedthroughs, SOI-MEMS devices, ENCAPSULATION, FABRICATION


This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au-Si eutectic bonding techniques. The dies sealed with anodic and Au-Si eutectic bonding provide a low vertical feedthrough resistance around 50 Omega. Glass-to-silicon anodically and Au-Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au-Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.