2.8 GHZ’de düşük faz gürültülü yük pompalı faz kilitlemeli döngü üzerine bir çalışma.

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Tezin Türü: Yüksek Lisans

Tezin Yürütüldüğü Kurum: Orta Doğu Teknik Üniversitesi, Mühendislik Fakültesi, Elektrik ve Elektronik Mühendisliği Bölümü, Türkiye

Tezin Onay Tarihi: 2016

Tezin Dili: İngilizce

Öğrenci: Mahsa Keykhali

Danışman: NEVZAT GÜNERİ GENÇER

Özet:

Today, the most challenging problem that Phase Locked Loop (PLL) designers face with is the design of ultra-low phase noise PLL at high frequencies. In this research, a high frequency charge-pump phase-locked loop (CPPLL) with low phase noise is studied. At the beginning stage, a gate grounding Colpitts Voltage Controlled Oscillator (VCO) using a High Electron Mobility Transistor (HEMT) is designed. The providedVCOachieved-131dBc/Hzat1MHzoffsetphasenoisewiththe2.6-3GHz oscillating frequency ranges. Inserting a PLL chip around the VCO can reduce the achieved phase noise. Therefore, to investigate this phenomenon a CPPLL is simulated. TheCPPLLcomponents,namelythePhaseFrequencyDetector(PFD),Charge Pump (CP), and the frequency divider are investigated individually. The loop filter design is also taken into account as it plays a vital role in determining the loop bandwidthoftheCPPLL.Finally,thephasenoiseoftheimplementedCPPLLissimulated. Assuming noiseless crystal oscillator, the phase noise is calculated as -120 dBc/Hz at 100 Hz offset. The phase noise is decreased successfully 90 dBc compared to the VCO phase noise (-32 dBc/Hz at 100 Hz). When the noise of the crystal oscillator is included, the phase noise at 100 Hz reached to -101 dBc/Hz. Related simulations are conducted on microwave simulation tool (ADS).