A high performance Sigma-Delta readout circuitry for mu g resolution microaccelerometers

Ocak I. E., Kepenek R., KÜLAH H., AKIN T.

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol.64, no.2, pp.137-145, 2010 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 64 Issue: 2
  • Publication Date: 2010
  • Doi Number: 10.1007/s10470-009-9433-4
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Page Numbers: pp.137-145
  • Keywords: Sigma-delta modulation, Switched capacitor readout circuit, Capacitive sensors, MEMS accelerometer
  • Middle East Technical University Affiliated: Yes


This paper reports a second order electromechanical sigma-delta readout for micro-g resolution accelerometers in addition to other high-sensitivity capacitive microsensors with large base capacitance. The chip implements a switched-capacitor readout front-end and an oversampled sigma-delta modulator, and hence can be used for both open-loop analog readout and closed-loop control and readout with direct digital output. The readout circuit has more than 115 dB dynamic range and can resolve less than 3 aF/root HHz. Also this IC includes start-up circuit and feedback mechanism for closed-loop control of the accelerometer with a single 5 V supply in a +/- 4 g range. Together with the accelerometer, bandwidth of the overall systemis limited with the sensor resonance frequency (1.53 kHz) in the open-loop mode. However in closed loop mode, oversampling of the acceleration data increases the bandwidth of the system up to few hundred kilohertz which is limited with the cut-off frequency of the low-pass filter placed at the output of the system. The start-up circuit allows rebalancing of a thick silicon proof mass with the limited 5 V supply after system start from power down or in the case of over-range input acceleration. The readout chip has been combined with a Silicon-On-Glass lateral accelerometer, which has a high sensitivity of 1.88 pF/g with large proof mass and long finger structures. A digital filtration and decimation circuitry is also implemented to signal process the output bit stream of the readout circuit. The complete module consumes 16 mW from a +/- 2.5 V supply and has an adjustable sensitivity up to 8 V/g with a noise level of 4.8 mu g/ root Hz in open-loop.