Cmos LNA design for system-on-chip receiver stages

Telli A., Askar M.

Topical Meeting on Silicon Monolithic Intergrated Circuits in RF Systems, Georgia, Amerika Birleşik Devletleri, 8 - 10 Eylül 2004, ss.171-174 identifier identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Basıldığı Şehir: Georgia
  • Basıldığı Ülke: Amerika Birleşik Devletleri
  • Sayfa Sayıları: ss.171-174
  • Orta Doğu Teknik Üniversitesi Adresli: Hayır

Özet

In this study, narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for "System-on-Chip" receiver stages have been designed, simulated and compared using Mietec CMOS 0.7 mu m process and the Cadence/BSIM3v3 tool with active or L-biased DC-bias circuitries. Since there is an intension to use LNAs for GSM and S-band low earth orbit (LEO) space applications, the operating frequencies have been chosen as 900MHz, 2025 MHz and 2210 MHz.