Cmos LNA design for system-on-chip receiver stages

Telli A., Askar M.

Topical Meeting on Silicon Monolithic Intergrated Circuits in RF Systems, Georgia, United States Of America, 8 - 10 September 2004, pp.171-174, (Full Text) identifier identifier

  • Publication Type: Conference Paper / Full Text
  • City: Georgia
  • Country: United States Of America
  • Page Numbers: pp.171-174
  • Middle East Technical University Affiliated: No

Abstract

In this study, narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for "System-on-Chip" receiver stages have been designed, simulated and compared using Mietec CMOS 0.7 mu m process and the Cadence/BSIM3v3 tool with active or L-biased DC-bias circuitries. Since there is an intension to use LNAs for GSM and S-band low earth orbit (LEO) space applications, the operating frequencies have been chosen as 900MHz, 2025 MHz and 2210 MHz.