In this paper, we introduce the design of an IP processor core code-named CUSPARC for Cairo university SPARC processor. This core is a 32 bit pipelined processor that conforms to SPARC v8 ISA. It is complete with 4 register windows, I and D caches, SRAM and flash memory controller, resolution hardware for the data and branch hazards, interrupts and exception handling, instructions to support I/O transfers, and two standard WISHBONE buses to support high speed and low speed IO transfers. The design was downloaded and tested on different FPGA platforms, in addition to 0.35μm and 0.13μm ASIC technologies. CUSPARC has a promising metric of 0.9663 DMIPS/MHz. A novel debugger tool was developed for validating CUSPARC. This tool facilitates the testing of the processor running complex software loads by invoking Mentor's MODELSIM simulator in the background while maintaining a "simulator-like" GUI in the foreground. © 2009 IEEE.