An Efficient Iterative SIC for Full-Duplex SC-FDE Radio Under Hardware Impairments


KURT A. , Salman M. B. , Satana H. A. , GÜVENSEN G. M.

IEEE International Conference on Communications (ICC), ELECTR NETWORK, 14 - 23 June 2021 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/icc42927.2021.9500602
  • Country: ELECTR NETWORK
  • Keywords: Turbo DSIC, nonlinear DSIC, SELF-INTERFERENCE CANCELLATION, MEMORY

Abstract

In this study, a novel iterative turbo digital self interference cancellation (DSIC) algorithm is proposed to eliminate remaining self interference (SI) signal, which is contaminated by signal of interest (SoI), subject to time varying SI channel. SoI creates a noise floor for the estimation of SI signal; hence, estimation accuracy significantly degrades. In order to improve the estimation accuracy, it is proposed that for each block, SoI is decoded via signal decomposition based on generalized memory polynomial (GMP) and neural network (NN) nonlinear regressors and its copy subtracted from received signal iteratively so that SoI contamination is decreased. This procedure is performed in an online manner during data transmission stage; therefore, it does not yield extra training overhead. In addition, since each block is processed independently, the proposed algorithm can track varying channel efficiently. Both numerical results and hardware implementations are presented to demonstrate the effectiveness of the proposed algorithm.