Dynamic body-biasing is a well studied approach for reducing the leakage power in memory systems. Proposed designs dynamically change the body bias of the inactive memory cells in order to tune their threshold voltages. However, prior body biasing schemes only focus on the static power reduction and overlook the power dissipation stemmed from the short circuit current. Recent studies showed that the neglected short circuit power became significant fraction of the overall power consumption in CMOS circuits. On the other hand, conventional short circuit power optimization techniques are not appropriate for the memory cells due to the area and performance constraints. In this study, we propose a supplementary body biasing scheme to address the short circuit current issue of the SRAM cells. We contend that the technique can easily be adapted to many former body-bias schemes and enables significant short circuit current reduction with slight performance impact.