The Effects of Gate-Connected Field Plates on Hotspot Temperatures of AlGaN/GaN HEMTs

Dundar C., Kara D., Donmezer N.

IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.67, no.1, pp.57-62, 2020 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 67 Issue: 1
  • Publication Date: 2020
  • Doi Number: 10.1109/ted.2019.2953123
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Academic Search Premier, Aerospace Database, Applied Science & Technology Source, Business Source Elite, Business Source Premier, Communication Abstracts, Compendex, Computer & Applied Sciences, INSPEC, Metadex, Civil Engineering Abstracts
  • Page Numbers: pp.57-62
  • Keywords: Electrothermal modeling, field plates, GaN high electron mobility transistors (HEMTs), Joule heating, passivation, BREAKDOWN VOLTAGE, THERMAL CHARACTERIZATION, CHANNEL TEMPERATURE, GAN HEMTS, SUBSTRATE, SILICON, DEVICES, HFET
  • Middle East Technical University Affiliated: Yes


To increase the reliability and the maximum performance of AlGaN/GaN high electron mobility transistors (HEMTs), gate field plates are frequently used with surface passivation. Although significant research has been done to understand the electrical effects of gate field plates on devices, their thermal effects are still not fully understood. For this purpose, electrothermal simulations are performed on devices with and without gate field plates having different thicknesses of Si3N4 surface passivation at two different biasing conditions. These simulations prove that more than 8 reduction of maximum temperature can be achieved with the use of gate field plates on devices operated at ${P}={4}$ W/mm. Field plates, when used in multifinger device configurations, have a greater impact on the outermost fingers' temperatures and can be used to achieve temperature uniformity. Surface passivation studies suggest that while thick passivation layers (200 nm in case of Si3N4) eliminate the thermal advantages of the field plate technology, very thin passivation layers (45 nm) cause an increase in the electric field and a decrease in the breakdown voltage. Thus, significant thermal advantages can be achieved when gate field plates are introduced following a field plate length and passivation thickness optimization based on the device biasing conditions.