PCB Layout Based Short-Circuit Protection Scheme for GaN HEMTs

Alemdar O. S. , KARAKAYA F. , KEYSAN O.

11th Annual IEEE Energy Conversion Congress and Exposition (ECCE), Maryland, Amerika Birleşik Devletleri, 29 Eylül - 03 Ekim 2019, ss.2212-2218 identifier identifier

  • Cilt numarası:
  • Doi Numarası: 10.1109/ecce.2019.8913081
  • Basıldığı Şehir: Maryland
  • Basıldığı Ülke: Amerika Birleşik Devletleri
  • Sayfa Sayıları: ss.2212-2218


Gallium Nitride Enhancement-Mode High Electron Mobility Transistors (GaN HEMTs) are superior to other power transistors in terms of efficiency, package size and switching speed which leads to increased power density in power converter applications. However, GaN HEMTs have much shorter short-circuit withstand time compared to the conventional devices, which is limited to several hundred nanoseconds. Therefore, reliable and fast protection solutions are required to protect GaN HEMTs from fatal over-current failures. In this paper, a novel short-circuit (SC) protection scheme based on fault current sensing by using Printed Circuit Board (PCB) layout parasitics is proposed. The proposed scheme uses the voltage drop on the parasitic inductance of the PCB trace to detect very intense high slew rate SC faults. In addition, the voltage drop on the parasitic resistance of the PCB trace is utilized to detect relatively slow over-current (OC) faults. Once a fault is detected, a soft turn-off mechanism is initiated by the proposed circuit to turn-off devices gradually to eliminate over-voltage breakdown risk. The proposed circuit is verified by both SPICE simulations and hardware implementation. The experimental results show that both SC and OC faults can be detected and GaN HEMTs can be protected. The total operation duration for the circuit is 370 ns during a SC fault. The SC fault can be detected within 30 ns and the soft turn-off mechanism is initiated within 80 ns to terminate the SC current flowing through the GaN HEMTs within 290 ns.