IP address lookup modules for backbone routers should store 100Ks of entries, find the longest prefix match (LPM) for each incoming packet at 10s of Gbps line speed and support thousands of lookup table (LUT) updates each second. It is desired that these updates are non-blocking, that is without disrupting the ongoing lookups. Furthermore, considering the increasing line rates and table sizes, the scalability of the design is very important. Ternary content-addressable memory (TCAM) architectures are widely deployed for hardware IP lookup. In this paper, we propose a novel TCAM architecture, S-DIRECT-Scalable and Dynamically REConfigurable TCAM, that is custom designed for hardware IP lookup. S-DIRECT consists of hierarchically combined TCAM cells with inherent priority encoders (PEs) to support LPM. Hence, its design is scalable without any need for a separate PE or a redesign for different table size. Furthermore, S-DIRECT can perform constant time, non-blocking updates in hardware provided that certain write capabilities are present in the TCAM entries. S-DIRECT architecture is both independent of the hardware platform and the implementation of the TCAM cells. We demonstrate the generality and viability of S-DIRECT by implementing it both with prefix/mask register and LUT-based TCAM cells on FPGA.