A low-power switched-current algorithmic A/D converter

Tezel A., Akin T.

1999 IEEE International Symposium on Circuits and Systems (ISCAS 99), Florida, United States Of America, 30 May - 02 June 1999, pp.282-285 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • City: Florida
  • Country: United States Of America
  • Page Numbers: pp.282-285

Abstract

This paper reports the development of a low-power switched-current algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter uses modified (SI)-I-2 type current copiers to reduce the overall area and power consumption. The analog portion of the converter occupies only 0.35mm(2) area in 3 mu m CMOS technology. The simulation results show that the converter provides 10 bits resolution with a conversion rate of 61kHz, while dissipating only 1mW power from a single 5V supply.