A low-power switched-current algorithmic A/D converter

Tezel A., Akin T.

1999 IEEE International Symposium on Circuits and Systems (ISCAS 99), Florida, Amerika Birleşik Devletleri, 30 Mayıs - 02 Haziran 1999, ss.282-285 identifier identifier

  • Basıldığı Şehir: Florida
  • Basıldığı Ülke: Amerika Birleşik Devletleri
  • Sayfa Sayıları: ss.282-285

Özet

This paper reports the development of a low-power switched-current algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter uses modified (SI)-I-2 type current copiers to reduce the overall area and power consumption. The analog portion of the converter occupies only 0.35mm(2) area in 3 mu m CMOS technology. The simulation results show that the converter provides 10 bits resolution with a conversion rate of 61kHz, while dissipating only 1mW power from a single 5V supply.