IEEE INFOCOM Conference, Florida, Amerika Birleşik Devletleri, 25 - 30 Mart 2012, ss.1898-1906, (Tam Metin Bildiri)
Hierarchical search structures for packet classification offer good memory performance and support quick rule updates when implemented on multi-core network processors. However, pipelined hardware implementation of these algorithms has two disadvantages: (1) backtracking which requires stalling the pipeline and (2) inefficient memory usage due to variation in the size of the trie nodes.