Scalable High-Throughput FPGA Architecture for SMAC Message Authentication Code
23rd International Conference on Security and Cryptography, SECRYPT 2026, Porto, Portekiz, 16 - 18 Temmuz 2026, ss.96-107, (Tam Metin Bildiri)
- Yayın Türü: Bildiri / Tam Metin Bildiri
- Doi Numarası: 10.5220/0015062600004103
- Basıldığı Şehir: Porto
- Basıldığı Ülke: Portekiz
- Sayfa Sayıları: ss.96-107
- Anahtar Kelimeler: FPGA, Hardware Acceleration, Message Authentication Code, Scalable Architecture, SMAC
- Orta Doğu Teknik Üniversitesi Adresli: Evet
Özet
SMAC is a recently proposed by Wang et al. stand-alone Message Authentication Code (MAC) constructed from repeated applications of the AES round function and featuring an aggregation mode, SMAC-1×n, for scalable parallel processing. Although originally designed for high-throughput CPU implementations leveraging AES-NI instructions, its structural properties suggest strong compatibility with hardware parallelism. However, no systematic FPGA-oriented architectural study of SMAC has been reported. This paper presents a scalable FPGA architecture of SMAC implemented on a Xilinx Kintex UltraScale+ KCU116 platform. The Π transformation is evaluated in a single clock cycle using fully combinational AES rounds, and throughput scaling is achieved through physical replication of aggregation lanes. All SMAC-1×n configurations up to n = 16 are implemented and evaluated. Post-implementation results achieve maximum operating frequencies up to 526 MHz and peak throughput of 731 Gbps for SMAC-1×16. The design exhibits near-linear throughput scaling up to eight lanes and reaches a maximum efficiency of 24.5 Mbps/slice. These results demonstrate that SMAC’s round-based construction is well suited for FPGA parallelism and enables competitive high-throughput hardware MAC acceleration.