Hardware Accelerators for Cloud Computing: Features and Implementation

Tirlioglu A., Demir O. B., Yazar A., Schmidt E. G.

29th IEEE Conference on Signal Processing and Communications Applications (SIU), ELECTR NETWORK, 9 - 11 June 2021 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/siu53274.2021.9478015
  • Keywords: hardware accelerator, Canny edge detection, FPGA, cloud computing
  • Middle East Technical University Affiliated: Yes


In this paper, hardware accelerator (FHA) applications realized on FPGA that can be offered as a service in cloud computing systems are discussed. It is necessary to know the hardware resources used by FHA applications and the performance they provide for the efficient meeting of the user requests and effective resource planning. To this end, the first contribution of this paper is to provide a compilation of the literature on the features of frequently used hardware accelerators (matrix multiplication, face detection, FFT) in the last three years, based on common parameters and metrics. The numerical values we provide can be used for cloud resource allocation and creation of sample cloud workloads. The second contribution of our paper is the implementation of the Canny edge detector, a sample hardware accelerator implemented in HLS (High-level Synthesis), using an open source library. In this way, the work flow for the implementation and operation of the hardware accelerator together with its performance are presented.