Heterogeneous integration facilitates faster design cycles with optimal functional IP module and silicon node combinations, but requires ultra-high bandwidth for the die-to-die communications. Fine pitch interconnects can meet such high bandwidth demands with simpler circuits, lower power and less latency. Hence, it is of utmost importance to understand the performance of these interconnects at different speeds and channel lengths. This paper focuses on a parametric study over the basic design parameters of a generic fine pitch interconnect, to explore the electrical performance limits. As a result of this study, practical guidelines are provided for the die-to-die channel design.