Application of bit-level pipelining to delay insensitive null convention adders


Ismailoglu A. N. , Askar M.

IEEE International Symposium on Circuits and Systems, Louisiana, United States Of America, 27 - 30 May 2007, pp.3259-3260 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/iscas.2007.378167
  • City: Louisiana
  • Country: United States Of America
  • Page Numbers: pp.3259-3260

Abstract

In this study, two asynchronous delay insensitive adder topologies in Null Convention Logic [1] style are adopted for bit-level pipelining: The reduced Null Convention Logic Adder [2] and a Null Convention Carry Save Adder. When pipelined at bit-level, early carry generation feature of both adders violate the requirements of delay insensitivity. To solve this problem, new topologies are proposed. Resultant adders maintain both reliable delay insensitive operation and speedup advantages of early carry generation, with O(log n) average completion time for n-bit addition and -as a result of bit-level pipelining- constant throughput against increased bit-length.