Power-Delay Analysis of an ABACUS Parallel Integer Multiplier VLSI Implementation


Ercan F., Muhtaroglu A.

5th International Conference on Energy Aware Computing Systems & Applications (ICEAC), Cairo, Egypt, 24 - 26 March 2015 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Cairo
  • Country: Egypt

Abstract

ABACUS parallel architecture was previously proposed as an alternate integer multiplication approach with column compression and parallel carry futures. This paper presents a VLSI implementation for ABACUS and benchmarks it against the conventional Wallace Tree Multiplier (WTM). Simulations are conducted with UMC180nm technology in Cadence environment. Although WTM implementation results in 26.6% fewer devices, ABACUS implementation has 8.6% less power dissipation with matched delay performance, due to 27.8% lower average activity.