28th Signal Processing and Communications Applications Conference, SIU 2020, Gaziantep, Türkiye, 5 - 07 Ekim 2020
© 2020 IEEE.In this paper, we propose a scalable on-chip packet switch architecture for hardware accelerated cloud computing systems. Our proposed switch architecture is implemented on the FPGA and interconnects reconfigurable regions, 40 Gbps Ethernet interfaces and a PCIe interface. The switch fabric operates at line speed to achieve scalability. We propose a new algorithm that grants access to the fabric according to the allocated prioritization to input-output port pairs. The switch is implemented on Xilinx Zynq 7000-SoC and can work at 40 Gbps rate. Our simulation results show that our proposed algorithm achieves desired prioritization without degrading the throughput.