IMPLEMENTATION OF GAIN CONTROL AS IP CORE

Karabalkan M. A., Ermis E., Oner M.

24th Signal Processing and Communication Application Conference (SIU), Zonguldak, Türkiye, 16 - 19 Mayıs 2016, ss.321-324 identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Basıldığı Şehir: Zonguldak
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.321-324
  • Orta Doğu Teknik Üniversitesi Adresli: Evet

Özet

Stable output level increases the accuracy of further signal processing algorithms. So, gain control algorithms are important preprocessing steps. On the other hand, implementation of gain control algorithms vary depending on environment and performance parameters. In this case, the algorithms are required re-implementation. Re-implementation is a time consuming process especially for embedded signal processing platforms like FPGA. Implementation of signal processing algorithms as IP Cores are recommended to resolve re-design requirement. IP core is a logical block that is designed for FPGAs. By means of transportable structure, it can be applied to all systems easily. This paper presents implementation of gain control algorithms as IP Core. Introduced IP Core makes it easy to implement AGC and TVG in any conliguration. Also, it accelerates design time.