This paper presents a novel RC-triggered, field-effect transistor (FET)-based power clamp that can be used in high-voltage complementary metal oxide semiconductor (CMOS) processes. A simple two-stage design provides a fast trigger while keeping the clamp transistor on for much longer than the triggering duration without the need for an additional digital latching circuit. As the presented technique does not require any digital circuits, it is especially useful in bipolar-CMOS-DMOS (BCD) processes, where the implementation of digital blocks is difficult due to the limited gate to-source voltage of the laterally diffused metal oxide semiconductor (LDMOS) transistors. The proposed architecture is implemented in a 0.25-mu m BCD process offered by TSMC. Simulation results show that Class 3A-level electrostatic discharge (ESD) protection can be achieved with an 8-mm-wide device while keeping all gate-to-source voltage values below the recommended 5-V limit. As the circuit operation depends on the well-modeled transient behavior of transistors, the proposed technique can be extended to other ESD ratings and can also be migrated to other processes without the need of extensive hardware verification.