A High Performance PWM Algorithm for Common Mode Voltage Reduction in Three-phase Voltage Source Inverters

Uen E., HAVA A. M.

39th IEEE Power Electronic Specialists Conference (PESC 08), Rhodes, Greece, 15 - 19 June 2008, pp.1528-1534 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/pesc.2008.4592154
  • City: Rhodes
  • Country: Greece
  • Page Numbers: pp.1528-1534
  • Middle East Technical University Affiliated: Yes


A high performance PWM algorithm with reduced common mode voltage (CMV) and satisfactory overall performance is proposed for three-phase PWM inverter drives. The algorithm combines the near state PWM (NSPWM) method which has superior overall performance characteristics at high modulation index and MAZSPWM, a modified form of the active zero state PWM method (AZSPWM1), which is suitable for low modulation index range of operation. Since AZSPWM1 has line-to-line voltage pulse reversals with small zero-voltage time intervals, in its naive form it causes overvoltages, in particular in long cable motor drive applications. Obtained by re-organizing the duty cycles of the utilized voltage vectors of AZSPWM1, MAZSPWM has sufficiently long zero-voltage time intervals between pulse reversals such that overvoltages are avoided. The combined algorithm performs satisfactorily throughout the inverter operating range and the transition from NSPWM to MAZSPWM and vice versa is seamless. The performance of the proposed algorithm is proven by theory, computer simulations, and detailed laboratory experiments. The paper also shows that the proposed reduced CMV PWM algorithm is effective in reducing the motor leakage current and it is most beneficial when a small common mode inductor is included in the drive.