A Phase Coherent 7-bit Digital Step Attenuator on 0.18 mu m SOI

Jarihani A. E., Kocer F.

12th European Microwave Integrated Circuits Conference (EuMIC), Nuremberg, Germany, 8 - 10 October 2017, pp.167-170 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Nuremberg
  • Country: Germany
  • Page Numbers: pp.167-170
  • Keywords: Digital step attenuator, phase coherent attenuator, SOI, high linearity and power handling attenuator, phased array systems, CMOS, SHIFT
  • Middle East Technical University Affiliated: Yes


We present a novel digital step attenuator (DSA) with low phase variation under attenuation state and frequency changes. This is achieved while keeping all other specifications comparable with the state-of-the-art. To compensate the phase shift, a number of switchable phase compensating blocks are employed. Unlike previous studies, this work achieves very low phase variation in a commercial, 4x4 quad-flat no-leads (QFN) package, where wirebond effects are significant. The proposed attenuator has 7-bit control with 0 to 31.75 dB attenuation range with 0.25 dB step sizes and achieves accurate attenuation settings in a wide frequency range. The attenuator is fabricated in a commercial 0.18 mu m RF silicon-on-insulator (SOI) process. The measurement results show that the attenuator has an amplitude error of less than 1 dB, while introducing a maximum of +/- 3 degrees phase shift up to 2.2 GHz and less than +/- 6 degrees between 2.2-3.5 GHz. This approach provides at least 2.5-fold improvement in the phase shift when compared to commercial attenuators. The input 1 dB compression point and IIP3 are measured typically higher than 35 dBm and 45 dBm, respectively. Total chip size, including pads, is 1.95mm X 0.95mm.