Implementation and performance of parallellised turbo decoders

Erdin E., Kilcioglu C., YILMAZ A.

IET COMMUNICATIONS, cilt.5, sa.1, ss.39-50, 2011 (SCI-Expanded) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 5 Sayı: 1
  • Basım Tarihi: 2011
  • Doi Numarası: 10.1049/iet-com.2009.0647
  • Dergi Adı: IET COMMUNICATIONS
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Sayfa Sayıları: ss.39-50
  • Orta Doğu Teknik Üniversitesi Adresli: Evet

Özet

In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance and the data (information bit) rate. In order to decrease the latency a parallellised decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantisation scheme and normalisation in forward/backward recursions, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.