Hardware implementations of neural networks and the Random Neural Network Chip (RNNC)

Aybay I., Cerkez C., Halici U., Badaroglu M.

13th International Symposium on Computer and Information Sciences (ISCIS 98), BELEK ANTALYA, Turkey, 26 - 28 October 1998, vol.53, pp.157-161, (Full Text) identifier

  • Publication Type: Conference Paper / Full Text
  • Volume: 53
  • City: BELEK ANTALYA
  • Country: Turkey
  • Page Numbers: pp.157-161
  • Middle East Technical University Affiliated: Yes

Abstract

In this study, the basic properties of a number of important Neuro-chips, boards, and computers that have been physically produced shall be presented. Then, a digital MOS chip called RNNC, based on the random neural network model, shall be briefly discussed. The RNNC architecture is cascadable. The synapses of internal neurons within me chip are programmable. The RNNC circuit is implemented using the 0.7 mu m CMOS process.