Hardware implementations of neural networks and the Random Neural Network Chip (RNNC)

Aybay I., Cerkez C., Halici U., Badaroglu M.

13th International Symposium on Computer and Information Sciences (ISCIS 98), BELEK ANTALYA, Türkiye, 26 - 28 Ekim 1998, cilt.53, ss.157-161 identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Cilt numarası: 53
  • Basıldığı Şehir: BELEK ANTALYA
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.157-161
  • Orta Doğu Teknik Üniversitesi Adresli: Evet

Özet

In this study, the basic properties of a number of important Neuro-chips, boards, and computers that have been physically produced shall be presented. Then, a digital MOS chip called RNNC, based on the random neural network model, shall be briefly discussed. The RNNC architecture is cascadable. The synapses of internal neurons within me chip are programmable. The RNNC circuit is implemented using the 0.7 mu m CMOS process.