This paper presents a compact model for threshold self-compensated rectifiers that can be used to optimize circuit parameters early in the design phase instead of time-consuming transient simulations. A design procedure is presented for finding the optimum aspect ratio of transistors used in the converter and number of rectifying stages to achieve the maximum power conversion efficiency. In the presented analysis, the relation between the power conversion efficiency and the load current over the variation of the output dc voltage is used to find the optimum design parameters. Accurate approximation of the charge entering to and exiting from the rectifier during the steady state helps to get good agreement between the predicted output dc voltage and simulation results under different load current values. Using the Enz-Krummenacher-Vittoz model for the MOS transistor, an accurate formula is derived for optimization. The ability of the model in weak, moderate, and strong inversion region aids to find the optimum design parameters for broad range of RF voltage variation. The presented formula for estimating the optimum size and number of stages shows good agreement with simulations. Further validation is provided by comparing model predictions with measurement results of a four-stage self-compensated rectifier operating at 900 MHz, which is implemented in a commercial 0.18-mu m partially-depleted silicon-on-insulator process.