This paper introduces a detector biasing scheme proper for resistive microbolometer type uncooled thermal detector focal plane arrays (FPAs). The proposed scheme utilizes a 2-stage digital-to-analog converter (DAC) architecture where the first DAC stage generates the voltage interval that covers the bias voltage range of the overall FPA, while the second stage generates the high resolution analog voltages that are used to apply pixel-specific bias voltages. The second DAC stage output includes a resistive ladder type multi-level voltage generator (MLVG), which can be shared by multiple column readouts. The proposed scheme utilizes a single first stage DAC and a number of second stage DACs that can be optimized to meet the specifications of the application. The proposed scheme provides high resolution bias correction with small silicon area coverage, low power dissipation, and low noise. Furthermore, this scheme is suitable for microbolometer FPAs with very different detector resistance ranges, since the bias correction voltage interval is adjustable by the first DAC stage. The proposed architecture is used to design a 5+5 bit, 2-stage DAC that can be used in a 640x480 microbolometer FPA where a standard 0.35 mu m CMOS process is considered. The simulation results show that the circuit provides a detector current resolution of 130 nA when the architecture is optimized to cover a 80 k Omega nominal detector resistance with +/- 10% resistance nonuniformity. The designed circuit dissipates 7.5 mW with a single 5 V supply, and the noise contribution to the detector current is 30 pA for a 10 kHz electrical bandwidth.