Akademik Veri Yönetim Sistemi
22nd IEEE Signal Processing and Communications Applications Conference (SIU), Trabzon, Türkiye, 23 - 25 Nisan 2014, ss.1130-1133
The concept of partial reconfiguration has been introduced by leading FPGA vendors in recent years. Partial reconfiguration is a technique that allows to reprogram/reconfigure a specific part of an FPGA during run-time. This method allows switching between design modules that are not necessary to function at the same time without interrupting the FPGA's processing of the current task Hence larger designs can be implemented on the same FPGA. This work is an implementation of partial reconfiguration on an FPGA which is used as a hardware accelarator in a real-time target detection and tracking system. Run-time switching between different algorithm components became possible without interrupting the target detection and tracking capability of the overall system by using partial reconfiguration in the system. By this approach, FPGA resources are used efficiently and power consumption is reduced.