Counter and compressor circuits are key building blocks in digital processing. Much effort has been spent on optimization of individual compression circuits based on traditional performance evaluation metrics, such as compression ratio (C-R). More recently used C-R/Gate-Delay metric reflects compression capability and performance of compression blocks simultaneously, but it does not give an insight into power consumption, which is a vital parameter in contemporary systems with prevailing battery life and power efficiency constraints. This paper proposes a new evaluation measure that incorporates energy consumption: C-R/PDP. This metric is then used to evaluate compression circuits based on simulated power delay product or PDP. Proposed C-R/PDP metric showed that (2,3,3) counter is not as efficient as 4:2 and 5:2 compressor. Similarly, (6,3) and (12,4) are not as efficient as (7,3) and (13,4) respectively when PDP is considered. These properties cannot be detected using the previous C-R/Gate-Delay metric.