CMOS planar spiral inductor modeling and low noise amplifier design

Telli A., Demir Ş., Askar M.

MICROELECTRONICS JOURNAL, vol.37, no.1, pp.71-78, 2006 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 37 Issue: 1
  • Publication Date: 2006
  • Doi Number: 10.1016/j.mejo.2005.06.019
  • Journal Name: MICROELECTRONICS JOURNAL
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Page Numbers: pp.71-78
  • Keywords: RFIC, CMOS, low noise amplifier, planar spiral inductors, inductor modeling
  • Middle East Technical University Affiliated: Yes

Abstract

During this study, various narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for GSM and S-band low earth orbit (LEO) space applications have been designed, simulated and compared using Mietec CMOS 0.7 mu m process and the Cadence/BSIM3v3. To get more realistic results, parasitic effects due to layout have been calculated and added to the simulations. Also, considering the inductive source degenerative topology, most of the attention is given on the modeling of planar spiral inductor by lumped element circuits. Moreover to decrease the substrate effects, the inductors have been surrounded by grounded guard rings and have patterned ground shield (PGS) under them. The simulation results of LNA including the parasitic effects indicate a forward gain of 9 dB with noise figure of 4.5 dB while drawing 18 mW from + 3 V supply at 22 10 MHz. The area occupied is 1.8 mm X 1.6 mm with pads, 1.3 mm X 1.2 mm without pads. (c) 2005 Elsevier Ltd. All rights reserved.