A low-power analog-to-digital converter integrated circuit for data acquisition applications

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Tezin Türü: Yüksek Lisans

Tezin Yürütüldüğü Kurum: Orta Doğu Teknik Üniversitesi, Mühendislik Fakültesi, Elektrik ve Elektronik Mühendisliği Bölümü, Türkiye

Tezin Onay Tarihi: 2016

Öğrenci: SERHAT KOÇAK

Danışman: TAYFUN AKIN

Özet:

Data acquisition systems have been used in different kinds of applications such as sensing applications, wireless communication, and healthcare. Each of these applications requires a different and unique system in order to achieve high quality acquisition. These different and unique systems employ various components such as analog-to-digital converters, digital-to-analog converters, and external electronics. Each of these components offers an optimal solution in order to satisfy the system requirements. Analog-to-digital converters known as ADCs are the main devices in the data acquisition systems which interface between the physical parameters and digital systems. Low power and high performance ADCs are preferable, since the systems are comprised of many components which lead to significant amount of power consumption. This thesis presents the design, and implementation of an analog-to-digital integrated circuit for low power data acquisition applications. 0.35 μm CMOS technology is used in order to implement the proposed ADC. In this thesis, different ADC topologies are investigated, and successive approximation register known as SAR ADC is chosen since, that structure which is low noise, dissipates low power at medium resolution, and medium speed. In this work, each part of the ADC is analyzed in order to design an optimal ADC structure. Low power solutions for the differential rail to rail comparator and digital-to-analog converter are proposed for high performance ADC. A flexible and programmable digital controller which consists of the successive approximation register is implemented in order to perform the binary search algorithm. An output serializer is employed in order to reduce the number of pads. A programmable bias generator is designed to provide bias currents to the analog blocks. The designed chip occupies 2mmx2mm silicon area, and the power dissipation of the core of the designed chip is less than 1 mW which is suitable for low power data acquisition applications. The performance of the SAR ADC is evaluated based on the simulation results which conclude that, the designed SAR ADC is a promising solution for the low power data acquisition applications. A compact test setup including a compact PCB card, a FPGA card and a PC is designed for performing the ADC characterization tests.