Thesis Type: Doctorate
Institution Of The Thesis: Orta Doğu Teknik Üniversitesi, Faculty of Engineering, Department of Electrical and Electronics Engineering, Turkey
Approval Date: 2013
Student: AMİN RONAGHZADEH
Supervisor: ŞİMŞEK DEMİRAbstract:
Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power ampliﬁer and linearizer design techniques. Dynamically varying the load impedance and bias point of a transistor according to the varying envelope of the incoming RF signal also known as Dynamic Load Modulation (DLM) and Dynamic Supply Modulation (DSM), respectively, are two separate methods for improving the efficiency in power amplifier design. In this dissertation, a combination of both variable gate bias and tunable load concepts is applied in an amplifier structure consisting of two transistors in parallel. A novel computer aided design methodology is proposed for careful selection of the load and biasing points of the individual transistors. The method which is based on load-pull analysis performs sweeps on the gate bias voltages of the active devices and input drive level of the amplifier in order to obtain ranges of biases that result in the generation of IMD sweet spots. Following that, the amplifier is designed employing the load line theory and bias switching at the same time in order to enhance the efficiency in reduced drive levels while extending the output 1 dB compression point to higher values at higher drives. Tunable matching networks are implemented utilizing varactor stacks in a Π conﬁguration at the input and output of the amplifier. The amplifier starts to operate in the ﬁrst state where lowest possible bias levels are chosen for both of the transistors and the output matching network is adjusted to provide PAE matching. As approaching towards the higher output powers, the amplifier switches between different consecutive operational states per about 1 dB increment at output power. In this way, the maximum output P1dB can be attained from the amplifier. The operational states are selected among a bunch of possible states obtained from the load-pull analysis, based on providing smaller leaps in transition between states in PAE and gain curves. In order to validate the proposed design methodology, a 2.4 GHz medium-power amplifier is designed, fabricated and tested which demonstrates the feasibility of the proposed structure and design technique for power amplifier applications.