Design and implementation of low phase noise phase locked loop based local oscillator

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Tezin Türü: Yüksek Lisans

Tezin Yürütüldüğü Kurum: Orta Doğu Teknik Üniversitesi, Mühendislik Fakültesi, Elektrik ve Elektronik Mühendisliği Bölümü, Türkiye

Tezin Onay Tarihi: 2009

Öğrenci: MUHSİN ALPEREN BÖLÜCEK

Danışman: ŞİMŞEK DEMİR

Özet:

In this thesis, a low phase noise local oscillator operating at 2210 MHz is designed and implemented to be used in X-Band transmitter of a LEO satellite. Designed local oscillator is a PLL (Phase Locked Loop) based frequency synthesizer which is implemented using discrete commercial components including ultra low noise voltage controlled oscillator and high resolution, low noise fractional-N synthesizer. Operational settings of the synthesizer are done using three wire serial interface of a microcontroller. Although there are some imperfections in the implementation, phase noise of the prototype system is pretty good which is measured as -123.2 dBc/Hz at 100 kHz offset and less than -141.3 dBc/Hz at 1 MHz offset. Made up of discrete components, the VCO used in the designed local oscillator is not integrable to frequency synthesizer which is implemented in CMOS technology. Considering technological progress, integrabilitiy of system components becomes important for designing single chip complete systems like transmitters, receivers or transceivers. Therefore considering a potential single chip transceiver production, also a CMOS voltage controlled oscillator is designed using standard TSMC 0.18um technology operating in between 2.05 GHz and 2.35 GHz . Since low phase noise is the main concern, phase noise models and phase noise reduction techniques that are derived from the models are studied. These techniques are applied to the VCO core to see the effects. Design is finalized by applying some of those techniques which are found to be noticeably effective to the core design. Finalized core operates from 2.15 GHz to 2.25 GHz and phase noise is simulated as -107.265 dBc/Hz at 100 kHz offset and -131.167 dBc/Hz at 1 MHz offset. Also oscillator has figure of merit of -185.4 at 100 kHz offset. These values show that designed core is considerably good when compared to similar designs.