Cmos class e power amplifier modelling and design including channel resistance effects

Thesis Type: Postgraduate

Institution Of The Thesis: Middle East Technical University, Faculty of Engineering, Department of Electrical and Electronics Engineering, Turkey

Approval Date: 2004

Thesis Language: English

Student: İbrahim Demir

Supervisor: ŞİMŞEK DEMİR


CMOS is the favorite candidate process for the high integration of the wireless communication IC blocks, RF frontend and digital baseband circuitry. Also the design of the RF power amplifier stage is the one of the most important part of the RF CMOS circuit design. Since high frequency and high power simultaneously exists on this stage, devices works on the limits of the process. Therefore standard device models may not be valid enough for a successful design. In the thesis high frequency passive device and MOS transistor models for the CMOS process searched though the literature and presented. Besides, different structures of the inductors are investigated for the best quality factor for the chosen process. Class E power amplifiers can reach very high efficiencies and they are very suitable for the low power applications. After the derivation of the classical Class E equations is presented, a new Class E circuit model including MOS transistor̕s channel resistance is developed and new sets of equations are obtained for the model. Circuit parameters are determined using numerical methods. Class E circuit simulations with these new parameters and earlier parameters are compared. Finally, a 100mW 2.4GHz Class E power amplifier is designed and simulated targeting Bluetooth applications. In this design, Class E circuit parameters are determined for AMS CMOS 0.35um process MOS transistor including the channel resistance. Simulations are performed using Cadence/BSIM3v3 and OrCad PSPICE.