Yesil, S. Et Al. 2019. Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion. 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , (Genoa, Italy), 614-617.

Yesil, S., Sen, C., & YILMAZ, A. Ö., (2019). Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion . 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp.614-617). Genoa, Italy

Yesil, Soner, Cansu Sen, And ALİ ÖZGÜR YILMAZ. "Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion," 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genoa, Italy, 2019

Yesil, Soner Et Al. "Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion." 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , Genoa, Italy, pp.614-617, 2019

Yesil, S. Sen, C. And YILMAZ, A. Ö. (2019) . "Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion." 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , Genoa, Italy, pp.614-617.

@conferencepaper{conferencepaper, author={Soner Yesil Et Al. }, title={Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion}, congress name={26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)}, city={Genoa}, country={Italy}, year={2019}, pages={614-617} }