Yancinkaya, B. And Aydın Göl, E. 2019. Clock Reduction in Timed Automata While Preserving Design Parameters. 2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) , (Montreal, Canada).

Yancinkaya, B., & Aydın Göl, E., (2019). Clock Reduction in Timed Automata While Preserving Design Parameters . 2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE), Montreal, Canada

Yancinkaya, Beyazit, And EBRU AYDIN GÖL. "Clock Reduction in Timed Automata While Preserving Design Parameters," 2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE), Montreal, Canada, 2019

Yancinkaya, Beyazit And Aydın Göl, EBRU A. . "Clock Reduction in Timed Automata While Preserving Design Parameters." 2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) , Montreal, Canada, 2019

Yancinkaya, B. And Aydın Göl, E. (2019) . "Clock Reduction in Timed Automata While Preserving Design Parameters." 2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) , Montreal, Canada.

@conferencepaper{conferencepaper, author={Beyazit Yancinkaya And author={EBRU AYDIN GÖL}, title={Clock Reduction in Timed Automata While Preserving Design Parameters}, congress name={2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE)}, city={Montreal}, country={Canada}, year={2019}}